Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core

In this paper we present the design of a full encryptor/decryptor core for AES algorithm which fits in single-chip FPGA. Our design performs encryption, decryption and key scheduling. To increase performance, a pipelined architecture is being proposed. In addition, several modifications to standard AES algorithm’s formulations have introduced that allow us to obtain a significant reduction in the total number of computations and the path delay associated to them. Two approaches have been followed to implement the most costly step of AES, multiplicative inverse in GF(2). The first approach uses pre-computed values stored in a lookup table. The second approach simplifies computations to reduce memory requirements at the cost of increasing time. The obtained results indicate that both designs are competitive with the fastest complete AES FGPA core implementation reported to date. Our first approach requires up to 11.8% less CLB slices, 21.5% less BRAMs and yields up to 18.5% higher throughput than the fastest one.